Semiconductor circuits such as semiconductor memory devices have widely been used in various portable devices such as portable telephones. For the semiconductor circuits to be used for the portable devices, it is a great issue how to reduce the power consumption. Japanese laid-open patent publications Nos. 63-255897 and 11-16368 disclose prior arts for reducing the power consumption.
FIG. 1 is a block diagram showing a basic structure of a semiconductor memory device (DRAM: dynamic RAM) disclosed in Japanese laid-open patent publication No. 63-255897. The semiconductor memory device has a φ WL generating circuit 152 for generating a word line driving signal φ WL. The φ L generating circuit 152 receives an external input of /RAS signal (/ means a negative logic signal and RAS means a row address strobe), and generates the word line driving signal φ WL in accordance with the inputted /RAS signal. The semiconductor memory device also has a row decoder 155 which is connected to an output side of the φ WL generating circuit 152 and receives an input of the word line driving signal φ WL as outputted from the φ WL generating circuit 152. The semiconductor memory device also has a φ WL booster circuit 153 for boosting the word line driving signal φ WL as well as a φ WL comparator circuit 154. The φ WL comparator circuit 154 receives an external input of a reference voltage Vref and is connected to an output side of the φ WL generating circuit 152 for receiving the input of the word line driving signal φ WL as outputted from the φ WL generating circuit 152, whereby the φ WL comparator circuit 154 compares the word line driving signal φ WL and the reference voltage Vref and outputs a compared result signal S4 as a result of the comparison. Further, the φ WL booster circuit 153 receives an input of the /RAS signal and is connected to an output side of the φ WL comparator circuit 154 for receiving an input of the compared result signal S4, whereby the φ WL booster circuit 153 boosts the word line driving signal φ WL based on the /RAS signal and the compared result signal S4 from the φ WL comparator circuit 154. The row decoder 155 supplies the word line driving signal φ WL to a word line WL designated by the address signal.
Operations of the above circuit will be described based on the timing chart of FIG. 2. As the /RAS signal falls, the φ WL generating circuit 152 upon receipt of this /RAS signal makes the word line driving signal φ WL rise up to a power voltage level Vcc at a time “t1”. At the same time, the φ WL booster circuit 153 upon receipt of this /RAS signal makes the word line driving signal φ WL boost up to a higher level than Vcc. At a time “t2” where the /RAS signal falls, the φ WL comparator circuit 154 compares a level VWL of the word line driving signal φ WL and the reference voltage Vref, and outputs the signal S4 which shows the comparison result, which is supplied to the φ WL booster circuit 153. If VWL<Vref, then the φ WL booster circuit 153 boosts the word line driving signal φ WL. If VWL>Vref, then the φ WL booster circuit 153 does not boost the word line driving signal φ WL.
As described above, the circuit of FIG. 1 performs a boosting operation at the end of active cycle automatically if necessary but does not perform if unnecessary to reduce the power consumption by the circuit.
FIG. 3 is a block diagram showing a basic structure of a semiconductor memory device (SRAM: static RAM) disclosed in Japanese laid-open patent publication No. 11-16368. FIG. 4 is a timing chart describing operations of the semiconductor memory device. An ATD circuit 110 detects any transitions of address signals A0˜An or a chip select signal CE to generate a pulse signal φ OS. An XE generator circuit 111 receives inputs of the pulse signal φ OS which represents the address transition detection from the ATD circuit 110 and the chip select signal CE, and outputs a word line activation signal XE. The XE generator circuit 111 is free from the control by a write control signal /WE, for which reason operations with the signal XE are the same between the write and read cycles, and a high level output will be continued until a reset by the next signal φ OS due to the address transition in the next cycle. The row decoder 102 receives an input of a row address signal and outputs a row selecting signal which selects a word line.
A boost signal generator circuit 114 receives inputs of the word line activation signal XE and the write control signal /WE, and generates a boost signal /φ BEN which instructs the boost. Namely, in the write cycle where the write control signal /WE is low level, this boost signal generator circuit 114 continues to output the low level except for a reset time period, where the word line activation signal XE is in the low level. In the read cycle where the write control signal /WE is high level, this boost signal generator circuit 114 outputs the low level in a predetermined time period and subsequently outputs the high level.
A boost potential generating circuit 115 operates, if the boost signal /φ BEN is in the low level, to generate a boost voltage VBST which is supplied to a word driver 104. The word driver 104 is powered by the boost voltage VBST and selects a word line based on inputs of the word line activation signal XE and the row selecting signal, whereby a potential of the selected word line is risen up to the boost voltage VBST, and a write operation to memory cells or a read operation from memory cells is accomplished.
A sense amplifier activation signal generating circuit 112 receives inputs of the word line activation signal XE and the write control signal /WE, and outputs a sense amplifier activation signal φ SE. The sense amplifier activation signal φ SE is generated only in the read cycle, and becomes high level with a time delay after the word line is risen. This high level will be continued to keep a sense amplifier 106 in active state until a reset by the signal φ OS due to the address transition in the next cycle. The sense amplifier 106 receives an input of a signal on complementary digit lines DG, DGB selected by a column selecting switch 105 based on an output from a column decoder 103. The sense amplifier 106 performs an amplification of data from memory cells during when the sense amplifier activation signal φ SE is high level.
As described above, the circuit shown in FIG. 3 makes the boost potential generating circuit 115 operable only in an initial time period of the read cycle, but inoperable in other time periods than the initial time period of the read cycle, in order to reduce the power consumption by the boost potential generating circuit 115.
The prior art is to reduce the power for driving the word lines but does not disclose any other power reduction method.
In recent years, the pseudo SRAM has been developed and practiced. As well known, this pseudo SRAM has an advantage in such a large capacity as DRAM and another advantage in such usefulness as SRAM as well as still another advantage of a reduced power consumption in stand-by-state, for which reason the pseudo SRAM has been used widely to the portable devices. For use of this pseudo SRAM to the portable devices, however, a further reduction of the power consumption is desired.
FIG. 5 is a block diagram illustrative of a basic structure of a conventional pseudo SRAM. FIG. 6 is a timing chart describing operations of the pseudo SRAM. The pseudo SRAM has a voltage level control circuit 1, a memory cell array 2, a ring oscillator 3, a boost circuit 4, and a word decoder 5. Further, the pseudo SRAM has a row decoder 6, a refresh timing generator circuit 7 and a row enable generator circuit 8.
The voltage level control circuit 1 generates, based on reference voltages Vref1 and Vref2, an internal voltage level control signal A which controls a level of the boost voltage Vbt to be applied to a word line of the memory cell array 2. An input side of the ring oscillator 3 is connected to an output side of the voltage level control circuit 1, so that the internal voltage level control signal A is inputted into the ring oscillator 3. The ring oscillator 3 is an oscillating circuit and may comprise a series connection in ring-shape of odd number inverters. If the internal voltage level control signal A outputted from the voltage level control circuit 1 is “H” (high level), then the ring oscillator 3 is activated to output an oscillation output B.
An input side of the boost circuit 4 is connected to an output side of the ring oscillator 3 so that the oscillation output B is inputted into the boost circuit 4. The boost circuit 4 may comprise a charge pump circuit. The boost circuit 4 utilizes the output B from the ring oscillator 3 and boosts a power voltage VDD up by step-by-step and outputs a boost voltage Vbt which is to drive the word line. An output side of the boost circuit 4 is connected to the word decoder 5 so that the boost voltage Vbt is inputted into the word decoder 5. In this case, the boost voltage Vbt is higher than the power voltage VDD, for example, (VDD+1.5V) or (VDD+2V). The word decoder 5 is connected to an output side of the row decoder 6, so that the word decoder 5 supplies the boost voltage Vbt to a word line selected by an output from the row decoder 6. The memory cell array 2 is a memory cell array having the same structure as the memory cell array of DRAM.
The refresh timing generating circuit 7 generates, at a constant time interval, a refresh signal for refreshing memory cells in the memory cell array 2 and a refresh address for designating an address of the memory cell to be refreshed. An output side of the refresh timing generating circuit 7 is connected to the row enable generating circuit 8 so that the refresh signal is inputted into the row enable generating circuit 8 and also the refresh address is inputted into the row decoder 6.
The row enable generating circuit 8 receives inputs of a write enable signal WE, a chip select signal CS and a read/write address Add for the memory cell array 2. Upon change or transition of the address Add, the row enable generating circuit 8 generates a row enable signal LT. The row enable generating circuit 8 generates the signal LT at the time when the refresh timing generating circuit 7 outputs the refresh signal. An output of the row enable generating circuit 8 is connected to the row decoder 6 and the voltage level control circuit 1, so that the row enable signal LT is inputted into the voltage level control circuit 1 and the row decoder 6. Upon receipt of the input of the row enable signal LT, the row decoder 6 decodes the read/write address Add externally entered and supplies a decoded result to the word decoder 5.
FIG. 6 is a timing chart describing operations of the circuit shown in FIG. 5. After the write enable signal WE becomes “L” (low level) and the chip select signal Cs becomes “H”, then transition of the address Add causes that the row enable signal LT is outputted from the row enable generating circuit 8 and inputted into the voltage level control circuit 1. The voltage level control circuit 1 compares the boost voltage Vbt and the reference voltage Vref1. If the boost voltage Vbt is lower than the reference voltage Vref1, then the voltage level control circuit 1 makes the internal voltage level control signal A at “H” (high level) at the time “t1”. The high level “H” of the internal voltage level control signal A starts the oscillation of the ring oscillator 3 and the ring oscillator 3 outputs the oscillation output B. The oscillation output B is then inputted into the boost circuit 4. The boost circuit 4 uses the oscillation output B for boosting the boost voltage Vbt. As the boost voltage Vbt is risen and reaches the reference voltage Vref2, then the voltage level control circuit 1 makes the internal voltage level control signal A at “L” (low level) at the time “t2”, whereby the oscillation of the ring oscillator 3 is discontinued and boosting operation by the boost circuit 4 is thus discontinued.
As described above, in accordance with the conventional pseudo SRAM, the voltage level control circuit 1 activates the ring oscillator 3 and the boost circuit 4 only in the necessary time period but inactivates them in the unnecessary time period in order to reduce the power consumption.
The conventional semiconductor memory device, however, is designed for a power reduction of the circuit for generating a voltage to be applied to the memory cell array but does never for any power reduction of the voltage level control circuit 1 which controls the voltage to be applied to the memory cell array.
In accordance with the normal DRAM, the refresh timing is controlled by a system, and the device is needed to keep or hold always the boosted voltage level, for which reason it is unnecessary to reduce the power of the circuit for controlling the voltage to be applied to the memory cell array. There is no strict restriction to the power in the stand-by-state.
In contrast, the pseudo SRAM is needed for such a power reduction as many as SRAM. The pseudo SRAM is needed for a possible reduction of the power to be supplied to the voltage level control circuit. Namely, the pseudo SRAM is designed so that the refresh operation is invisible from an exterior of the device, wherein a refresh current is not considered in accordance with the regulation of the power consumption, for which reason the pseudo SRAM needs more strict regulations than the normal DRAM.